Integrated circuits incorporate complex electrical components formed in semiconductor material into a single device. Generally, an integrated circuit comprises a substrate upon which a variety of circuit components are formed wherein each of the circuit components are electrically isolated from each other. Integrated circuits are made of semiconductor material. Semiconductor material is material that has a resistance that lies between that of a conductor and an insulator. Semiconductor material is used to make electrical devices that exploit its resistive properties.
Semiconductor material is typically doped to be either a N type or a P type. N type semiconductor material is doped with a doping type impurity that generally conducts current via electrons. P type semiconductor material is doped with an acceptor-type impurity that conducts current mainly via hole migration. A N type or P type having a high impurity or high dopant concentration or density is denoted by a “+” sign. A N type of P type having a low impurity or low dopant concentration or density is denoted by a “−” sign.
One type of circuit component is a metal-oxide semiconductor (MOS) transistor. A transistor is a device used to amplify a signal or open and close a circuit. A typical transistor comprises a substrate having layers of varying semiconductor materials that form a source, a drain and a gate. An integrated circuit may comprise a plurality of transistors created from a single substrate to form a circuit.
MOS gated devices, including transistor devices formed in an integrated circuit, typically suffer from degraded performance in safe operating areas and unclamped inductive switching when parasitic bipolar components inherent in MOS gated devices approach their collector-emitter break down voltage (BVCEO). This can be referred to as parasitic bipolar transistor action. Double Diffused Metal Oxide Silicon (DMOS) transistors and Insulated Gate Bipolar Transistors (IGBT), are examples of MOS gated devices. For a NDMOS, the parasitic bipolar component is a NPN.
Referring to the NDMOS example, current can flow from a drain (N type) of the device through a body (P type) positioned under a source (N type) to a surface body contact. The voltage drop developed by this current flow can reach the turn on voltage for the body-source junction along a portion of the junction remote from the surface body contact. That portion of the body-source junction turns on and injects electrons across the body into the drain when the turn on voltage is reached. The blocking voltage of the device drops from proximately BVCBO of the parasitic NPN to approximately collector-emitter break down voltage (BVCEO) of the NPN. This is the basis for reduced performance. The relationship of the breakdown can be approximated by the equation BVCEO=BVCBO/(HFE)1/4. Wherein HFE represents a parasitic current gain of a bipolar transistor. HFE can also be referred to as beta. For example, for a parasitic NPN HFE=20, the BVCEO will be about ½ the BVCBO. By reducing the HFE, the parasitic bipolar transistor action is reduced thereby enhancing the performance of the device.
The degradation resulting from this parasitic action can be significant. One method of minimizing its impact is to include a P+ body contact region under a portion of the source that is not proximate a channel end of the source where it would cause an unacceptable increase in the threshold voltage. The P+ contact region reduces the resistance through which the current flows thereby increasing the current required to cause the degradation to occur. The use of the P+ contact region provides a useful improvement in device performance but further improvements are desired.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a MOS structure in an integrated circuit that has reduced parasitic HFE levels when the parasitic components are activated.